1. Field of the Invention
The present invention relates generally to phase-locked loop frequency synthesizers and more specifically, the invention relates to implementation of a PLL frequency synthesizer capable of fast lock-in operation at the instant immediately after frequency dividers are energized to operate a voltage controlled oscillator in a closed-loop mode. The present invention is particularly suitable for power saving PLL frequency synthesizers.
2. Description of the Related Art
Fast lock-in capability is an important feature of a phase-locked loop regardless of its application in order to recover from an out-of-phase condition. Power saving is another important feature of the phase-locked loop if it is used in portable radio receivers. Since power consumption of a PLL frequency synthesizer of a radio receiver accounts for a substantial proportion of its total power, battery supply of its two frequency dividers is periodically interrupted to operate its voltage-controlled oscillator in an open-loop mode. As shown and described in Japanese Laid-Open Patent Specification Sho-60-248022, energy stored in the lowpass (loop) filter during a closed-loop mode is utilized during the next open-loop mode to enable the VCO to produce its output. During the closed-loop mode, the input signals of the phase detector must be resynchronized, or locked in phase to each other even if they are synchronized in frequency. Since longer the time it takes for the closed-loop mode to resynchronize the shorter the time allowed for the open-loop mode to continue, it is desirable from the power savings view point that the two frequency dividers are locked in phase as quickly as possible.
Japanese Laid-Open Patent Specification Sho-64-1330 discloses a fast lock-in power-saving PLL frequency synthesizer whose resynchronization process is controlled by the use of two gate circuits as illustrated in FIG. 1. One of the gate circuits, indicated at 2, is connected in the circuit between a quartz oscillator 1 and a divided-by-M frequency divider 3, the other gate circuit 8 being connected in the circuit between a voltage-controlled oscillator 7 and a divide-by-N frequency divider 9. The scaling factor M is constant, while the scaling factor N is variable in accordance with an externally supplied frequency (channel) control signal. The phase difference between the outputs of the frequency dividers 3 and 9 is detected by a phase detector 4 and supplied through a switch 5 and a lowpass filter 7 to the VCO 7. To the outputs of the frequency dividers is connected a control circuit 10 to which power saving pulses are supplied from an external source. Although not shown in FIG. 1, power supply to the frequency dividers 3 and 9 is cut off and the switch 5 is turned off to operate the VCO 7 in an open-loop mode. Immediately after the frequency dividers are activated again, but before the switch 5 is turned on to operate the VCO in a closed loop mode, the control circuit 10 determines whether the frequency divider 9 is lagging or leading with respect to the frequency divider 3. Control circuit 10 turns off the gate circuit 2 if the divider 9 is lagging and turns off the gate circuit 8 if it is advancing. The length of the turn-off time of these gate circuits is determined so that the inputs of the phase detector 4 are aligned in phase with each other.
However, when one of the gate circuits is turned off, there is a possibility of one of the frequency dividers producing at least one error count, and there is also a possibility of another error count when the gate circuit is turned on. In the prior art, there is a likelihood of the occurrence of a maximum initial phase difference of two cycles. Therefore, the prior art approach is still not sufficient for fast lock-in operation because of imprecision timing control of the gate circuits.